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RF5189
0
Typical Applications * IEEE802.11B WLAN Applications * 2.5GHz ISM Band Applications * Wireless LAN Systems Product Description
The RF5189 is a linear, medium-power, high-efficiency amplifier IC designed specifically for battery-powered WLAN applications such as PC cards, mini PCI, and compact flash applications. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in 2.5GHz WLAN and other spread-spectrum transmitters. The device is provided in a 12-pin QFN package with a backside ground. The RF5189 is designed to maintain linearity over a wide range of supply voltage and power output. The RF5189 is designed to reduce end-product BOM count by integrating all matching circuitry onto the chip.
3.00
Pin 1 ID
A
3V, 2.45GHz LINEAR POWER AMPLIFIER
RoHS Compliant & Pb-Free Product * Commercial and Consumer Systems * Portable Battery-Powered Equipment * Spread-Spectrum and MMDS Systems
1.55 1.35
Pin 1 ID
0.50 TYP 3.00
0.15 C
2 PLCS
1.45
0.15 C
2 PLCS
B
0.45 TYP 0.25
0.10 M C A B
0.05
0.203 REF
0.1 C
0.08 C
0.925 0.775
Dimensions in mm.
0.102 REF
C
Shaded areas represent pin 1.
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS
Package Style: QFN, 12-Pin, 3x3
Features * Single Power Supply 3.0V to 5.0V * +30dBm Saturated Output Power * 25dB Small Signal Gain * High Linearity
VCC2
12
Input Match
VCC1
11
Interstage Match
10
Output Match
RF IN 1
VCC2
9 RF OUT
* 2400MHz to 2500MHz Frequency Range
NC 2
8 RF OUT
BIAS1GND 3
Bias
7 PWR SEN
Ordering Information
RF5189 RF5189 PCBA 3V, 2.45GHz Linear Power Amplifier Fully Assembled Evaluation Board
4 VREG1
5 VREG2
6 BIAS2GND
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev A7 060127
2-655
RF5189
Absolute Maximum Ratings Parameter
Supply Voltage Power Control Voltage (VREG) DC Supply Current Input RF Power Operating Ambient Temperature Storage Temperature Moisture sensitivity
Rating
-0.5 to +6.0 -0.5 to 3.5 600 +10 -40 to +85 -40 to +150 JEDEC Level 2
Unit
VDC V mA dBm C C
Refer to "Handling of PSOP and PSSOP Products" on page 16-15 for special handling information.
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall-11b Signal
Frequency Range Maximum Linear Output Power VCC =3.0V VCC =5.0V Linear Efficiency Small Signal Gain Second Harmonic 802.11B Adjacent Channel Power Alternate Channel Power Isolation Input Return Loss Output VSWR Power Detect Voltage
Specification Min. Typ. Max.
2400 to 2500
Unit
Condition
T=25C, VCC =3.0V, VREG =2.7V, Freq=2450MHz
MHz With 802.11B modulation (11Mbit/s) and meeting 802.11B spectral mask.
21 24 23
22 24 25 -38 -56 30 15.0 1.5:1 2.1 2.7 0
27 -35 -32 -52
dBm dBm % dB dBc dBc dBc dB dB V V V
PIN =-7dBm POUT =21dBm, VCC =3.0V POUT =21dBm, VCC =3.0V In "OFF" state, PIN =-5.0dBm 50 reference 50 reference P0 =21dBm Voltage supplied to control input; device is "ON" Voltage supplied to control input; device is "OFF"
9.5 2:1 1.7 2.1
2.4 3.0 0.5
Power Down
VREG "ON" VREG "OFF"
Power Supply
Operating Voltage Current Consumption 3.0 to 5.0 100 220 5 10 10 160 270 10 15 V A mA mA mA mA VREG =0V No RF input, VCC =3.0V, and VREG =2.7V POUT =21dBm, VCC =3.0V, and VREG =2.7V VCC =3.0V VCC =5.0V
VREG Current (Total)
2-656
Rev A7 060127
RF5189
Pin 1 Function RF IN Description
RF input. Input is matched to 50 and DC block is provided internally.
Interface Schematic
VCC1 INTERSTAGE MATCH INPUT MATCH
2 3 4
NC BIAS1GND VREG1
No connect. Recommend connecting to ground. Ground for first stage bias circuit. For best performance, keep traces physically short and connect immediately to ground plane. First stage input bias. This pin requires a regulated supply to maintain nominal bias current. See pin 4.
VREG1 BIAS VREG2
BIAS GND1
BIAS GND2
5 6 7 8
VREG2 BIAS2GND PWR SEN RF OUT
Second stage input bias. This pin requires a regulated supply to maintain nominal bias current. Usually connected to VREG1. Ground for second stage bias circuit. For best performance, connect to ground with a choke inductor. Provides an output voltage proportional to output RF level. RF output. Output is matched to 50 and DC block is provided internally.
See pin 4. See pin 4.
VCC2 OUTPUT MATCH
RF OUT
9 10 11 12 Pkg Base
RF OUT VCC2 VCC2 VCC1 GND
Same as pin 8. Second stage output bias. Supply should be connected through a choke inductor sized appropriately to handle the output bias current. Same as pin 10. First stage output bias. This pin is sensitive to bypass capacitors placed close to it. Place an RF short approximately 200mils from this pin before any other supply connections. Ground connection. The backside of the package should be connected to the ground plane through a short path (i.e., vias under the device will be required).
See pin 8. See pin 8. See pin 8. See pin 1.
Rev A7 060127
2-657
RF5189
Theory of Operation
The RF5189 is a two-stage device with a nominal gain of 25dB in the 2.4GHz to 2.5GHz ISM band. The RF5189 is designed primarily for IEEE802.11B WLAN applications where the available supply voltage and current are limited. This amplifier will operate to (and below) the lowest expected voltage made available by a typical PCMCIA slot in a laptop PC, and will maintain required linearity at decreased supply voltages. The RF5189 requires only a single positive supply of 3.0V nominal (or greater) to operate to full specifications. Power control is provided through two bias control input pins (VREG1 and VREG2), but in most applications these are tied together and used as a single control input. There is no external matching required on the input and output of the part, thus allowing minimal bill of material (BOM) parts count in end applications. Both the input and the output of the device are DC-blocked. For best results, the PA circuit layout from the evaluation board should be copied as closely as possible, particularly the ground layout and ground vias. Other configurations may also work, but the design process is much easier and quicker if the layout is copied from the RF5189 evaluation board. Gerber files of our designs are available on request. The RF5189 is not a difficult part to implement, but care in circuit layout and component selection is always advisable when designing circuits to operate at 2.5GHz. The choke inductors on VCC2 and BIAS2GND should be chosen so that they are parallel self-resonant at the frequency of operation. In addition, the supply side of the choke inductor on VCC2 should be bypassed with a capacitor that is series self-resonant at the frequency of operation. In practice, VCC1 and the supply side of the choke on VCC2 will be tied to the same supply. It is important to isolate VCC1 from other RF and low-frequency bypass capacitors on this supply line. This can be accomplished using a suitably-long transmission line which is RF shorted on the other end as described above. Ideally the length of this line will be a quarter wavelength, but it only needs to be long enough so that the effects of other supply bypass capacitors on the VCC1 line are minimized. If board space is a concern, this isolation can also be accomplished with an RF choke inductor or ferrite bead. The RF5189 has primarily been characterized with a voltage on VREG1 and VREG2 of 2.7VDC. However, the RF5189 will operate from a wide range of control voltages. If you prefer to use a control voltage that is significantly different than 2.7VDC, contact RFMD Sales or Applications Engineering for additional data and guidance.
2-658
Rev A7 060127
RF5189
Evaluation Board Schematic
VCC P1 C14 1 F L1 12 nH P1-1 1 2 P1-3 3 4 P1-5 12 J1 RF IN 50 strip 1
Input Match
PDETECT GND VREG2 GND VREG1
5 CON5
11
Interstage Match
10
Output Match
9 50 strip
P2 1 GND GND VCC1
2
8
J2 RF OUT
2 P2-3 3 CON3
3
Bias
7 C13 1000 pF 5 6 PDETECT P3-1 P3 1 VCC CON1 P4 1 GND CON1 C13 1000 pF L2 10 nH VREG2
4 C3 1000 pF
VREG1
Rev A7 060127
2-659
RF5189
Evaluation Board Layout Board Size 1.10" x 1.85"
Board Thickness 0.032", Board Material FR-4
2-660
Rev A7 060127
RF5189
30.0 28.0 26.0 24.0 22.0 300.0 350.0
POUT, Gain, ICC Total versus PIN (Typical) @ VCC=3.0V, VREG=2.7V 400.0
POUT, Gain, ICC Total versus VREG @ VCC=3.0V
27.0 26.0 25.0 24.0 250.0 300.0
Gain (dB), POUT (dBm)
Gain(dB), Pout(dBm)
20.0 18.0 16.0 200.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -20.0 -18.0 -16.0 -14.0 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 Pout(dBm) Gain(dB) ICC_Total(mA) 0.0 50.0 100.0 150.0
23.0 22.0 21.0
200.0
ICC Total (mA)
150.0 20.0 19.0 18.0 17.0 16.0 15.0 14.0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 Pout(dBm) Gain(dB) ICC_Total(mA) 0.0 50.0 100.0
PIN (dBm)
Vreq(V) POUT, PDETECT versus PIN (Typical) @ VCC=3.0, VREG=2.7 over Temp (-40, +25, +85)C
Pout(dBm) @ + 25 C 28.0 26.0 24.0 Pout(dBm) @ +85 c Pout(dBm) @ -40 C PDETECT (V) @ +25 C PDETECT (V) @ + 85 C 22.0 20.0 PDETECT (V) @ -40 C 3.5 4.0 4.5
Channel Frequency versus Gain (Typical) for VCC=3.0V,
3.3V, and 5.0V, VREG1=VREG2=2.7V and POUT=21dBm
30.0 30.0
5.0
29.0
28.0
27.0
POUT (dBm)
18.0 16.0
3.0
26.0
Gain (dB)
2.5 14.0 12.0 10.0 2.0
25.0
24.0 1.5 8.0 6.0 1.0
23.0
22.0
Gain(dB)@Vcc=3.0Volts Gain(dB)@Vcc=3.3Volts Gain(dB)@Vcc=5.0 Volts
4.0 0.5 2.0 0.0 -20.0 0.0 -2.0
21.0
20.0 2.412 2.417 2.422 2.427 2.432 2.437 2.442 2.447 2.452 2.457 2.462 2.467 2.472 2.477 2.482
-18.0
-16.0
-14.0
-12.0
Frequency (GHz)
PIN (dBm)
-10.0
-8.0
-6.0
-4.0
Rev A7 060127
2-661
PDETECT (V)
ICC Total (mA)
250.0
RF5189
300.0 280.0 260.0 240.0 220.0
ICQ, ICC_Total, POUT versus VREG (Typical) @ VCC=3.0V, PIN=5dBm
ICQ(mA) ICC_Total(mA) Pout(dBm)
IREG, POUT versus VREG (Typical) @ VCC=3.0V,
10.0 Ireg(mA) 9.0 Pout(dBm)
26.0 24.0 22.0
25.0
PIN=-5.0dBm
30.0 28.0
20.0
8.0 7.0
ICQ, ICC_Total (mA)
200.0
20.0
IREG_Total (mA)
POUT (dBm)
160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 1.6 1.7 1.8 1.9 2.0 2.1 2.2
0.0 5.0 10.0
16.0
5.0
14.0
4.0 3.0
12.0 10.0 8.0
2.0 1.0
6.0 4.0 2.0
0.0 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
0.0
2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
3.0
VREG (V)
VREG (V)
Spectral Mask (Typical): VCC=3.0V, VREG1=VREG2=2.7V, POUT=18dBm, PIN=-7.55dBm, and ICC_Total=168mA
Spectral Mask (Typical): VCC=3.0V, VREG1=VREG2=2.7V, POUT=21dBm, PIN=-4.0dBm, and ICC_Total=210mA
2-662
Rev A7 060127
POUT (dBm)
180.0
15.0
6.0
18.0
RF5189
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.69 x 0.28 (mm) Typ. B = 0.28 x 0.69 (mm) Typ. C = 1.45 (mm) Sq. 1.00 Typ.
Pin 12 Dimensions in mm.
B
Pin 1
B
B
Pin 9
A 0.50 Typ. A A 0.78 Typ. B B B
Pin 6
A C A A 1.00 Typ.
0.78 Typ. 0.50 Typ.
Figure 1. PCB Metal Land Pattern (Top View)
Rev A7 060127
2-663
RF5189
PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB Metal Land Pattern with a 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.79 x 0.38 (mm) Typ. B = 0.38 x 0.79 (mm) Typ. C = 1.55 (mm) Sq. 1.00 Typ.
Pin 12 Dimensions in mm.
B
Pin 1
B
B
Pin 9
A 0.50 Typ. A A 0.78 Typ. B B B
Pin 6
A C A A 1.00 Typ.
0.78 Typ. 0.50 Typ.
Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB Metal Land Pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
2-664
Rev A7 060127

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